Halide 22.0.0 Halide compiler and libraries

mini_hexagon_dma.h
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1// This header declares the Hexagon DMA API, without depending on the Hexagon SDK.
2
3#ifndef MINI_HEXAGON_DMA_H
4#define MINI_HEXAGON_DMA_H
5
6#ifdef __cplusplus
7extern "C" {
8#endif
9
10 typedef uint16_t uint16;
11 typedef uint32_t uint32;
12 typedef int32_t int32;
13 typedef unsigned long addr_t;
14
15 typedef unsigned int qurt_size_t;
16 typedef unsigned int qurt_mem_pool_t;
17#define HALIDE_HEXAGON_ENUM enum __attribute__((aligned(4)))
18
19__inline static int align(int x, int a) {
20 return ((x + a - 1) & (~(a - 1)));
21}
22
23HALIDE_HEXAGON_ENUM{QURT_EOK = 0};
24
25/**
26 * Power Corner vote
27 */
28#define PW_MIN_SVS 0
29#define PW_SVS2 1
30#define PW_SVS 2
31#define PW_SVS_L1 3
32#define PW_NORMAL 4
33#define PW_NORMAL_L1 5
34#define PW_TURBO 6
35
36/**
37 * Format IDs
38 */
39typedef HALIDE_HEXAGON_ENUM{
40 eDmaFmt_RawData,
41 eDmaFmt_NV12,
42 eDmaFmt_NV12_Y,
43 eDmaFmt_NV12_UV,
44 eDmaFmt_P010,
45 eDmaFmt_P010_Y,
46 eDmaFmt_P010_UV,
47 eDmaFmt_TP10,
48 eDmaFmt_TP10_Y,
49 eDmaFmt_TP10_UV,
50 eDmaFmt_NV124R,
51 eDmaFmt_NV124R_Y,
52 eDmaFmt_NV124R_UV,
53 eDmaFmt_Invalid,
54 eDmaFmt_MAX,
55} t_eDmaFmt;
56
57/**
58 * DMA status
59 * Currently not use, for future development
60 */
61 typedef void *t_stDmaWrapperDmaStats;
62
63/**
64 * Transfer type
65 */
66 typedef HALIDE_HEXAGON_ENUM eDmaWrapper_TransationType{
67 /// DDR to L2 transfer
68 eDmaWrapper_DdrToL2,
69 /// L2 to DDR transfer
70 eDmaWrapper_L2ToDdr,
71} t_eDmaWrapper_TransationType;
72
73/**
74 * Roi Properties
75 */
76 typedef struct stDmaWrapper_Roi {
77 /// ROI x position in pixels
78 uint16 u16X;
79 /// ROI y position in pixels
80 uint16 u16Y;
81 /// ROI width in pixels
82 uint16 u16W;
83 /// ROI height in pixels
84 uint16 u16H;
85} t_StDmaWrapper_Roi;
86
87/**
88 * Frame Properties
89 */
90 typedef struct stDmaWrapper_FrameProp {
91 /// Starting physical address to buffer
92 addr_t aAddr;
93 /// Frame height in pixels
94 uint16 u16H;
95 /// Frame width in pixels
96 uint16 u16W;
97 /// Frame stride in pixels
98 uint16 u16Stride;
99} t_StDmaWrapper_FrameProp;
100
101/**
102 * Roi alignment
103 */
104 typedef struct stDmaWrapper_RoiAlignInfo {
105 /// ROI width in pixels
106 uint16 u16W;
107 /// ROI height in pixels
108 uint16 u16H;
109} t_StDmaWrapper_RoiAlignInfo;
110
111/**
112 * DmaTransferSetup Properties
113 */
114 typedef struct stDmaWrapper_DmaTransferSetup {
115 /// Frame Width in pixels
116 uint16 u16FrameW;
117 /// Frame height in pixels
118 uint16 u16FrameH;
119 /// Frame stride in pixels
120 uint16 u16FrameStride;
121 /// ROI x position in pixels
122 uint16 u16RoiX;
123 /// ROI y position in pixels
124 uint16 u16RoiY;
125 /// ROI width in pixels
126 uint16 u16RoiW;
127 /// ROI height in pixels
128 uint16 u16RoiH;
129 /// ROI stride in pixels
130 uint16 u16RoiStride;
131 /// Virtual address of the HW descriptor buffer (must be locked in the L2$).
132 void *pDescBuf;
133 /// Virtual address of the TCM pixeldata buffer (must be locked in the L2$).
134 void *pTcmDataBuf;
135 /// Virtual address of the DDR Frame buffer .
136 void *pFrameBuf;
137 // UBWC Format
138 uint16 bIsFmtUbwc;
139 /// Should the intermediate buffer be padded. This only apply for 8bit format sucha NV12, NV12-4R
140 uint16 bUse16BitPaddingInL2;
141 /// Format
142 t_eDmaFmt eFmt;
143 /// TransferType: eDmaWrapper_DdrToL2 (Read from DDR), eDmaWrapper_L2ToDDR (Write to DDR);
144 t_eDmaWrapper_TransationType eTransferType;
145} t_StDmaWrapper_DmaTransferSetup;
146
147/**
148 * Abstraction for allocation of memory in cache and lock
149 *
150 * @brief API for Cache Allocation
151 *
152 * @return NULL or Memory
153 */
154 void *HAP_cache_lock(unsigned int size, void **paddr_ptr);
155
156/**
157 * Abstraction for deallocation of memory and unlock cache
158 *
159 * @brief API for Free
160 *
161 * @return void
162 */
163 int HAP_cache_unlock(void *vaddr_ptr);
164
165/**
166 * Handle for wrapper DMA engine
167 */
168 typedef void *t_DmaWrapper_DmaEngineHandle;
169
170/**
171 * Allocates a DMA Engine to be used by using the default wait type (polling).
172 *
173 * @brief Allocates a DMA Engine to be used
174 *
175 * @return Success: Engine's DMA Handle
176 * @n Failure: NULL
177 */
178 extern t_DmaWrapper_DmaEngineHandle hDmaWrapper_AllocDma(void);
179
180/**
181 * Frees a DMA Engine that was previously allocated by AllocDma().
182 *
183 * @brief Frees a DMA Engine
184 *
185 * @param[in] hDmaHandle - Engine's DMA Handle
186 *
187 * @return Success: OK
188 * @n Failure: ERR
189 */
190 extern int32 nDmaWrapper_FreeDma(t_DmaWrapper_DmaEngineHandle hDmaHandle);
191
192/**
193 * Starts a transfer on the provided DMA engine. The transfer is based
194 * on descriptors constructed in earlier nDmaWrapper_Prepare() and
195 * nDmaWrapper_Update() calls.
196 *
197 * @brief Starts a transfer request on the DMA engine
198 *
199 * @param[in] hDmaHandle - Engine's DMA Handle
200 *
201 * @return Success: OK
202 * @n Failure: ERR
203 */
204 extern int32 nDmaWrapper_Move(t_DmaWrapper_DmaEngineHandle hDmaHandle);
205
206/**
207 * Blocks until all outstanding transfers on the DMA are complete.
208 * The wait type is based on the type specified when allocating the
209 * engine.
210 *
211 * @brief Waits for all outstanding transfers on the DMA to complete
212 *
213 * @param[in] hDmaHandle - Engine's DMA Handle
214 *
215 * @return Success: OK
216 * @n Failure: ERR
217 */
218 extern int32 nDmaWrapper_Wait(t_DmaWrapper_DmaEngineHandle hDmaHandle);
219
220/**
221 * This call flushes the DMA buffers. Blocks until the flush of the DMA is complete.
222 *
223 * @brief Cleans up all transfers and flushes DMA buffers
224 *
225 * @param[in] hDmaHandle - Engine's DMA Handle
226 *
227 * @return Success: OK
228 * @n Failure: ERR
229 */
230 extern int32 nDmaWrapper_FinishFrame(t_DmaWrapper_DmaEngineHandle hDmaHandle);
231
232/**
233 * Get the recommended walk ROI width and height that should
234 * be used if walking the entire frame. The ROI returned is always
235 * in terms of frame dimensions. This function is different from
236 * nDmaWrapper_GetRecommendedRoi() as coordinates are not used.
237 *
238 * @brief Get the recommended walk ROI width and height
239 *
240 * @param[in] eFmtId - Format ID
241 * @param[in] bIsUbwc - Is the format UBWC (TRUE/FALSE)
242 * @param[in,out] pStWalkSize - Initial walk size, will be overwritten with
243 * the recommended walk size to align with DMA
244 * requirements
245 *
246 * @return Success: OK
247 * @n Failure: ERR
248 */
249 extern int32 nDmaWrapper_GetRecommendedWalkSize(t_eDmaFmt eFmtId, bool bIsUbwc,
250 t_StDmaWrapper_RoiAlignInfo *pStWalkSize);
251
252/**
253 * Calculates the HW descriptor buffer size based on the formats
254 * that will be used with the engine.
255 *
256 * @brief Get the HW descriptor buffer size per DMA engine
257 * @param[in] aeFmtId - Array of format IDs, such as eDmaFmt_NV12, eDmaFmt_NV12_Y,
258 * eDmaFmt_NV12_UV etc..
259 * @param[in] nsize - Number of format IDs provided
260 *
261 * @return Descriptor buffer size in bytes
262 */
263 extern int32 nDmaWrapper_GetDescbuffsize(t_eDmaFmt *aeFmtId, uint16 nsize);
264
265/**
266 * Get the recommended (minimum) intermediate buffer stride for the
267 * L2 Cache that is used transfer data from/to DDR. The stride is
268 * greater than or equal to the width and must be a multiple of 256.
269 *
270 * @brief Get the recommended intermediate buffer stride.
271 *
272 * @param[in] eFmtId - Format ID
273 * @param[in] pStRoiSize - The ROI that will be used (should be aligned with
274 * the DMA requirements for the format)
275 * @param[in] bIsUbwc - Is the format UBWC (TRUE/FALSE)
276 *
277 * @return Success: The intermediate buffer stride in pixels
278 * @n Failure: ERR
279 */
280 extern int32 nDmaWrapper_GetRecommendedIntermBufStride(t_eDmaFmt eFmtId,
281 t_StDmaWrapper_RoiAlignInfo *pStRoiSize,
282 bool bIsUbwc);
283
284/**
285 * Get the recommended intermediate buffer size for the L2 cache
286 * that is used to transfer data to/from DDR.
287 *
288 * @brief Get the recommended intermediate buffer size
289 *
290 * @param[in] eFmtId - Format ID
291 * @param[in] bUse16BitPaddingInL2 - Is padding to 16 bits done in the L2 (TRUE/FALSE)
292 * @param[in] pStRoiSize - The ROI that will be used (should be aligned with
293 * DMA requirements for the format). The Chroma ROI must
294 * follow the standing convention that the provided
295 * width and height must be specified in terms of the
296 * Luma plane also such that when the width is divided
297 * by 2 it specifies the number of interleaved Chroma
298 * pixels.
299 * @param[in] bIsUbwc - Is the format UBWC (TRUE/FALSE), note that this should
300 * be set to TRUE if either the DDR input or output will
301 * be UBWC
302 * @param[in] u16IntermBufStride - The stride (in pixels) to use, the minimum
303 * stride may be obtained by calling
304 * nDmaWrapper_GetRecommendedIntermBufStride
305 *
306 * @return Success: The intermediate buffer size in bytes
307 * @n Failure: ERR
308 */
309 extern int32 nDmaWrapper_GetRecommendedIntermBufSize(t_eDmaFmt eFmtId, bool bUse16BitPaddingInL2,
310 t_StDmaWrapper_RoiAlignInfo *pStRoiSize,
311 bool bIsUbwc, uint16 u16IntermBufStride);
312
313/**
314 * Setup Dma transfer parameters required to be ready to make DMA transfer.
315 * call this API multiple to create a descriptor link list
316 *
317 * @brief Dma transfer parameters per HW descriptor
318 *
319 * @param[in] hDmaHandle - Wrapper's DMA Handle. Represents t_StDmaWrapper_DmaEngine.
320 * @param[in] stpDmaTransferParm - Dma Transfer parameters. Each element describes
321 * complete Frame/ROI details for this Dma transfer
322 *
323 * @return Success: OK
324 * Failure: ERR
325 */
326 extern int32 nDmaWrapper_DmaTransferSetup(t_DmaWrapper_DmaEngineHandle hDmaHandle, t_StDmaWrapper_DmaTransferSetup *stpDmaTransferParm);
327
328/**
329 * DMA power voting based on Cornercase
330 *
331 * @brief DMA power voting based on Cornercase
332 *
333 * @param[in] cornercase:
334 * \code{.cpp}
335 * #define PW_MIN_SVS 0
336 * #define PW_SVS2 1
337 * #define PW_SVS 2
338 * #define PW_SVS_L1 3
339 * #define PW_NORMAL 4
340 * #define PW_NORMAL_L1 5
341 * #define PW_TURBO 6
342 * \endcode
343 *
344 * @return Success: OK
345 * @n Failure: ERR
346 */
347 extern int32 nDmaWrapper_PowerVoting(uint32 cornercase);
348
349#ifdef __cplusplus
350}
351#endif
352
353#endif
t_stDmaWrapperDmaStats
void * t_stDmaWrapperDmaStats
DMA status Currently not use, for future development.
Definition: mini_hexagon_dma.h:61
eDmaWrapper_TransationType
HALIDE_HEXAGON_ENUM eDmaWrapper_TransationType
Transfer type.
Definition: mini_hexagon_dma.h:66
t_StDmaWrapper_RoiAlignInfo
struct stDmaWrapper_RoiAlignInfo t_StDmaWrapper_RoiAlignInfo
Roi alignment.
nDmaWrapper_GetRecommendedIntermBufSize
int32 nDmaWrapper_GetRecommendedIntermBufSize(t_eDmaFmt eFmtId, bool bUse16BitPaddingInL2, t_StDmaWrapper_RoiAlignInfo *pStRoiSize, bool bIsUbwc, uint16 u16IntermBufStride)
Get the recommended intermediate buffer size for the L2 cache that is used to transfer data to/from D...
qurt_mem_pool_t
unsigned int qurt_mem_pool_t
Definition: mini_hexagon_dma.h:16
t_StDmaWrapper_Roi
struct stDmaWrapper_Roi t_StDmaWrapper_Roi
Roi Properties.
nDmaWrapper_FinishFrame
int32 nDmaWrapper_FinishFrame(t_DmaWrapper_DmaEngineHandle hDmaHandle)
This call flushes the DMA buffers.
nDmaWrapper_FreeDma
int32 nDmaWrapper_FreeDma(t_DmaWrapper_DmaEngineHandle hDmaHandle)
Frees a DMA Engine that was previously allocated by AllocDma().
t_StDmaWrapper_DmaTransferSetup
struct stDmaWrapper_DmaTransferSetup t_StDmaWrapper_DmaTransferSetup
DmaTransferSetup Properties.
t_DmaWrapper_DmaEngineHandle
void * t_DmaWrapper_DmaEngineHandle
Handle for wrapper DMA engine.
Definition: mini_hexagon_dma.h:168
qurt_size_t
unsigned int qurt_size_t
Definition: mini_hexagon_dma.h:15
addr_t
unsigned long addr_t
Definition: mini_hexagon_dma.h:13
HAP_cache_lock
void * HAP_cache_lock(unsigned int size, void **paddr_ptr)
Abstraction for allocation of memory in cache and lock.
hDmaWrapper_AllocDma
t_DmaWrapper_DmaEngineHandle hDmaWrapper_AllocDma(void)
Allocates a DMA Engine to be used by using the default wait type (polling).
nDmaWrapper_PowerVoting
int32 nDmaWrapper_PowerVoting(uint32 cornercase)
DMA power voting based on Cornercase.
nDmaWrapper_GetDescbuffsize
int32 nDmaWrapper_GetDescbuffsize(t_eDmaFmt *aeFmtId, uint16 nsize)
Calculates the HW descriptor buffer size based on the formats that will be used with the engine.
nDmaWrapper_DmaTransferSetup
int32 nDmaWrapper_DmaTransferSetup(t_DmaWrapper_DmaEngineHandle hDmaHandle, t_StDmaWrapper_DmaTransferSetup *stpDmaTransferParm)
Setup Dma transfer parameters required to be ready to make DMA transfer.
nDmaWrapper_Wait
int32 nDmaWrapper_Wait(t_DmaWrapper_DmaEngineHandle hDmaHandle)
Blocks until all outstanding transfers on the DMA are complete.
int32
int32_t int32
Definition: mini_hexagon_dma.h:12
nDmaWrapper_Move
int32 nDmaWrapper_Move(t_DmaWrapper_DmaEngineHandle hDmaHandle)
Starts a transfer on the provided DMA engine.
t_StDmaWrapper_FrameProp
struct stDmaWrapper_FrameProp t_StDmaWrapper_FrameProp
Frame Properties.
nDmaWrapper_GetRecommendedWalkSize
int32 nDmaWrapper_GetRecommendedWalkSize(t_eDmaFmt eFmtId, bool bIsUbwc, t_StDmaWrapper_RoiAlignInfo *pStWalkSize)
Get the recommended walk ROI width and height that should be used if walking the entire frame.
uint16
uint16_t uint16
Definition: mini_hexagon_dma.h:10
uint32
uint32_t uint32
Definition: mini_hexagon_dma.h:11
HALIDE_HEXAGON_ENUM
#define HALIDE_HEXAGON_ENUM
Format IDs.
Definition: mini_hexagon_dma.h:17
nDmaWrapper_GetRecommendedIntermBufStride
int32 nDmaWrapper_GetRecommendedIntermBufStride(t_eDmaFmt eFmtId, t_StDmaWrapper_RoiAlignInfo *pStRoiSize, bool bIsUbwc)
Get the recommended (minimum) intermediate buffer stride for the L2 Cache that is used transfer data ...
HAP_cache_unlock
int HAP_cache_unlock(void *vaddr_ptr)
Abstraction for deallocation of memory and unlock cache.
Halide::Runtime::Internal::Qurt::QURT_EOK
@ QURT_EOK
Definition: mini_qurt.h:10
int32_t
signed __INT32_TYPE__ int32_t
Definition: runtime_internal.h:24
uint16_t
unsigned __INT16_TYPE__ uint16_t
Definition: runtime_internal.h:27
uint32_t
unsigned __INT32_TYPE__ uint32_t
Definition: runtime_internal.h:25
stDmaWrapper_DmaTransferSetup
DmaTransferSetup Properties.
Definition: mini_hexagon_dma.h:114
stDmaWrapper_DmaTransferSetup::u16RoiX
uint16 u16RoiX
ROI x position in pixels.
Definition: mini_hexagon_dma.h:122
stDmaWrapper_DmaTransferSetup::pTcmDataBuf
void * pTcmDataBuf
Virtual address of the TCM pixeldata buffer (must be locked in the L2$).
Definition: mini_hexagon_dma.h:134
stDmaWrapper_DmaTransferSetup::u16RoiY
uint16 u16RoiY
ROI y position in pixels.
Definition: mini_hexagon_dma.h:124
stDmaWrapper_DmaTransferSetup::eTransferType
t_eDmaWrapper_TransationType eTransferType
TransferType: eDmaWrapper_DdrToL2 (Read from DDR), eDmaWrapper_L2ToDDR (Write to DDR);.
Definition: mini_hexagon_dma.h:144
stDmaWrapper_DmaTransferSetup::u16RoiStride
uint16 u16RoiStride
ROI stride in pixels.
Definition: mini_hexagon_dma.h:130
stDmaWrapper_DmaTransferSetup::pDescBuf
void * pDescBuf
Virtual address of the HW descriptor buffer (must be locked in the L2$).
Definition: mini_hexagon_dma.h:132
stDmaWrapper_DmaTransferSetup::u16RoiH
uint16 u16RoiH
ROI height in pixels.
Definition: mini_hexagon_dma.h:128
stDmaWrapper_DmaTransferSetup::u16FrameStride
uint16 u16FrameStride
Frame stride in pixels.
Definition: mini_hexagon_dma.h:120
stDmaWrapper_DmaTransferSetup::bUse16BitPaddingInL2
uint16 bUse16BitPaddingInL2
Should the intermediate buffer be padded. This only apply for 8bit format sucha NV12,...
Definition: mini_hexagon_dma.h:140
stDmaWrapper_DmaTransferSetup::bIsFmtUbwc
uint16 bIsFmtUbwc
Definition: mini_hexagon_dma.h:138
stDmaWrapper_DmaTransferSetup::u16FrameH
uint16 u16FrameH
Frame height in pixels.
Definition: mini_hexagon_dma.h:118
stDmaWrapper_DmaTransferSetup::u16RoiW
uint16 u16RoiW
ROI width in pixels.
Definition: mini_hexagon_dma.h:126
stDmaWrapper_DmaTransferSetup::pFrameBuf
void * pFrameBuf
Virtual address of the DDR Frame buffer .
Definition: mini_hexagon_dma.h:136
stDmaWrapper_DmaTransferSetup::u16FrameW
uint16 u16FrameW
Frame Width in pixels.
Definition: mini_hexagon_dma.h:116
stDmaWrapper_DmaTransferSetup::eFmt
t_eDmaFmt eFmt
Format.
Definition: mini_hexagon_dma.h:142
stDmaWrapper_FrameProp
Frame Properties.
Definition: mini_hexagon_dma.h:90
stDmaWrapper_FrameProp::u16W
uint16 u16W
Frame width in pixels.
Definition: mini_hexagon_dma.h:96
stDmaWrapper_FrameProp::aAddr
addr_t aAddr
Starting physical address to buffer.
Definition: mini_hexagon_dma.h:92
stDmaWrapper_FrameProp::u16Stride
uint16 u16Stride
Frame stride in pixels.
Definition: mini_hexagon_dma.h:98
stDmaWrapper_FrameProp::u16H
uint16 u16H
Frame height in pixels.
Definition: mini_hexagon_dma.h:94
stDmaWrapper_RoiAlignInfo
Roi alignment.
Definition: mini_hexagon_dma.h:104
stDmaWrapper_RoiAlignInfo::u16W
uint16 u16W
ROI width in pixels.
Definition: mini_hexagon_dma.h:106
stDmaWrapper_RoiAlignInfo::u16H
uint16 u16H
ROI height in pixels.
Definition: mini_hexagon_dma.h:108
stDmaWrapper_Roi
Roi Properties.
Definition: mini_hexagon_dma.h:76
stDmaWrapper_Roi::u16H
uint16 u16H
ROI height in pixels.
Definition: mini_hexagon_dma.h:84
stDmaWrapper_Roi::u16W
uint16 u16W
ROI width in pixels.
Definition: mini_hexagon_dma.h:82
stDmaWrapper_Roi::u16Y
uint16 u16Y
ROI y position in pixels.
Definition: mini_hexagon_dma.h:80
stDmaWrapper_Roi::u16X
uint16 u16X
ROI x position in pixels.
Definition: mini_hexagon_dma.h:78